Integrator-chain multiplier - Multiple-Valued Logic, 1990., Proceedings of the Twentieth International Symposium on

Switched-capacitor (SC) signal processing, :ing a sampled-data, analog-circuit technique, has a natural affinity to multiple-valued logic (MVL). Its simplicity in creating and manipulating signedsignals (in the form of voltage or charge) in any desired radix makes the SC topology a unique circuit technique for MVL implementation, especially when the base value is relatively high. In this paper, an MVL multiplier circuit scheme called the Integrator-Chain method is presented. This circuit scheme is particularly suited to the SC topology. The feasibility of circuit implementations of the Integrator-Chain Multiplier design in various number systems, including the sign-bit number representation, the R s and (R-1)'s complement representations and the signed-digit number (SDN) system, is discussed. In particular, it is demonstrated by simulation that a 4x4 multiplier circuit operating in a radix-7 SDN system has a size comparable to the simplest binary counterpart.